A NOVEL HIGH SPEED MAC-16X16 VEDIC MULTIPLIER USINGRIPPLECARRY ADDER ON FPGA

Authors

  • Vishnu Prasad Patidar Research scholar, Dept. of Electronics Engineering, Trinity Institute of Tech. & Research, Bhopal, Madhya Pradesh, India Author
  • Sourabh Sharma Assistant Professor, Dept. of Electronics Engineering, Trinity Institute of Tech. & Research, Bhopal, MadhyaPradesh, India Author

Keywords:

RIPPLE-CARRY (RC) ADDER, VEDIC-MULTIPLIER (VM), URDHAVA-TRIYAKBHYAMSUTRA, CARRY SELECT ADDER, VERILOG HDL, MULTIPLIER-ACCUMULATOR(MAC).

Abstract

Vedic mathematics is one of the earliest Indian system of mathematics that was rediscovered in the early20thcentury This paper proposes the design of high speed MAC-Vedic Multiplier, with the techniques of VedicMathematics that have been modified to get better performance using Ripple Carry adders. Ahigh speedprocessor depends very much on the multiplier as it is one of the solution hardware blocks in most digital signal processing systems in addition to in general processors. Vedic Mathematics has a unique techniqueof calculations based on sixteen Sutras. we presents design and implementation of high speed MAC-16x16bit Vedic multiplier architecture which is fairly different from the Conventional method of multiplication like addand shift. Further, the Verilog HDL coding of Urdhva Triyakbhyam Sutra for 16x16 bits multiplicationandripple carry adder is simulated and implemented on XilinxISE9.2i.

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Published

2016-06-30

Issue

Vol. 3 No. 6 (2016): June

Section

Articles