DESIGN OF CMOS 8-BIT PARALLEL ADDER ENERGY EFFICIENT STRUCTURE USING SR-CPL LOGIC STYLE

Authors

  • Aravinth. T. S Assistant Professor, Department of Electronics & Communication Engineering, Karpagam Academy of Higher Education (Deemed to be University), Coimbatore, Tamil Nadu, India Author
  • Sundar. R Assistant Professor, Department of Electrical & Electronics Engineering, Karpagam College of Engineering, Coimbatore, Tamil Nadu, India Author
  • Felix Muthu PG Scholar, Department of Electronics & Communication Engineering, Karpagam Academy of Higher Education (Deemed to be University), Coimbatore, Tamil Nadu, India Author

Keywords:

SR-CPL logic Styles, PDP, DPL, Pass Transistor Logic, Virtuoso Cadence Environment.

Abstract

We present high speed and low power 8-Bit parallel adder cells designed with modified SR-CPL logic styles
that had a reduced power delay product (PDP) as compared to the previous logics DPL and pass transistor
logic. We have carried out a comparison against other parallel adders reported as having a low PDP, in terms of
speed and power consumption. All the parallel adders were designed with a 0.18µ m CMOS technology
virtuoso cadence environment. Simulations of the circuit show that the proposed parallel adders have reduced
the power from 0.33mW to 0.24mW.

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Published

2017-06-30

Issue

Vol. 4 No. 6 (2017): June

Section

Articles